Philips Semiconductors

Product specification

SCN2681T

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

8

RDN

IP0–IP6

WRN

OP0–OP7

tPS

tPH

OLD DATA

NEW DATA

(a) INPUT PINS

tPD

(b) OUTPUT PINS

SD00101

Figure 5. Port Timing

SYMBOL

LIMITS

UNIT

SYMBOL

Min

Max

UNIT

Port input setup time before RDN low

0

ns

Port input hold time after RDN high

0

ns

Port output valid after WRN high

200

ns

NOTE:

1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

NOTES:

1.

INTRN or OP3-OP7 when used as interrupt outputs.

2.

The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching

test environment are pronounced and can greatly affect the resultant measurement.

VM

VOL +0.5V

VOL

WRN

OUTPUT

tIR

SD00102

Figure 6. Interrupt Timing

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

INTRN (or OP3–OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt)

200

ns

Write THR (TxRDY interrupt)

200

ns

Reset command (delta break interrupt)

200

ns

Stop C/T command (counter interrupt)

200

ns

Read IPCR (input port change interrupt)

200

ns

Write IMR (clear of interrupt mask bit)

200

ns