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SCC68692E1N40 Datasheet(PDF) 7 Page - NXP Semiconductors |
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SCC68692E1N40 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 30 page Philips Semiconductors Product specification SCC68692 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 7 AC CHARACTERISTICS1, 2, 4 SYMBOL FIGURE PARAMETER LIMITS UNIT SYMBOL FIGURE PARAMETER Min Typ3 Max UNIT Reset Timing tRES 1 RESET pulse width 200 ns Bus Timing5 tAS 4,5,6 A1–A4 setup time to CSN Low 10 ns tAH 4,5,6 A1–A4 hold time from CSN Low 100 ns tRWS 4,5,6 RWN setup time to CSN High 0 ns tRWH 4,5,6 RWN holdup time to CSN High 0 ns tCSW8 4,5,6 CSN High pulse width 160 ns tCSD9 4,5,6 CSN or IACKN High from DTACKN Low 20 ns tDD 4,5,6 Data valid from CSN or IACKN Low 175 ns tDA8 4 RDN Low to data bus active 15 ns tDF8 4,5,6 Data bus floating from CSN or IACKN High 125 ns tDI8 4 RDN High to data bus invalid 20 ns tDS 4,5,6 Data setup time to CLK High 100 ns tDH 4,5,6 Data hold time from CSN High 0 ns tDAL 4,5,6 DTACKN Low from read data valid 0 ns tDCR 4,5,6 DTACKN Low (read cycle) from CLK High 125 ns tDCW 4,5,6 DTACKN Low (write cycle) form CLK High 125 ns tDAH 4,5,6 DTACKN High from CSN or IACKN High 100 ns IDAT 4,5,6 DTACKN High impedance from CSN or IACKN High 125 ns tCSC7 4,5,6 CSN or IACKN setup time to clock High 90 ns Port Timing5 tPS 7 Port input setup time to CSN Low 0 ns tPH 7 Port input hold time from CSN High 0 ns tPD 7 Port output valid from CSN High 400 ns Interrupt Timing tIR10 6 INTRN (or OP3–OP7 when used as interrupts) negated from: Read RHR (RxRDY/FFULL interrupt) 300 ns Write THR (TxRDY interrupt) 300 ns Reset command (break interrupt) 300 ns Stop C/T command (counter interrupt) 300 ns Read IPCR (input port change interrupt) 300 ns Write IMR (clear of interrupt mask bit) 300 ns Clock Timing tCLK 7 X1/CLK High or Low time 100 ns fCLK11 7 X1/CLK frequency 0 3.6864 4 MHz tCTC 7 CTCLK (IP2) High or Low time 100 ns fCTC9 7 CTCLK (IP2) frequency 100 4 MHz tRX 7 RxC High or Low time 220 ns fRX9 7 RxC frequency (16X) (1X) 100 100 2 1 MHz MHz tTX 7 TxC High or Low time 220 ns fTX9 7 TxC frequency (16X) (1X) 0 0 2 1 MHz MHz Transmitter Timing tTXD 8 TxD output delay from TxC external clock input on IP pin 350 ns tTCS 8 Output delay from TxC low at OP pin to TxD data output 150 ns Receiver Timing tRXS 9 RxD data setup time before RxC high at external clock input on IP pin 240 ns tRXH 9 RxD data hold time after RxC high at external clock input on IP pin 200 ns NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters. |
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