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MAX9172ETA Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX9172ETA Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 12 page ESD Protection ESD protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The receiver inputs of the MAX9171/MAX9172 have extra protection against static electricity. These pins are protected to ±13kV without damage. The structures withstand ESD during normal operation and when powered down. The receiver inputs of these devices are characterized for protection to the limit of ±13kV using the Human Body Model. Human Body Model Figure 4a shows the Human Body Model, and Figure 4b shows the current waveform it generates when dis- charged into a low-impedance load. This model con- sists of a 100pF capacitor charged to the ESD test voltage, which is then discharged into the test device through a 1.5k Ω resistor. Applications Information Supply Bypassing Bypass VCC with high-frequency surface-mount ceram- ic 0.1µF and 0.001µF capacitors in parallel, as close to the device as possible, with the 0.001µF capacitor clos- est to the device. For additional supply bypassing, place a 10µF tantalum or ceramic capacitor at the point where power enters the circuit board. Differential Traces Input trace characteristics affect the performance of the MAX9171/MAX9172. Use controlled-impedance PCB traces to match the cable characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of traces. Each channel’s differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differ- ential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors Transmission media typically have a controlled differen- tial impedance of about 100 Ω. Use cables and connec- tors that have matched differential impedance to minimize impedance discontinuities. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. Termination The MAX9171/MAX9172 require an external termination resistor. The termination resistor should match the differ- ential impedance of the transmission line. Termination resistance values may range between 90 Ω to 132Ω, depending on the characteristic impedance of the transmission medium. When using the MAX9171/MAX9172, minimize the dis- tance between the input termination resistors and the MAX9171/MAX9172 receiver inputs. Use a single 1% surface-mount resistor. Board Layout For LVDS applications, a four-layer PCB that provides separate power, ground, LVDS signals, and output sig- nals is recommended. Separate the input LVDS signals from the output signals to prevent crosstalk. Solder the exposed pad on the TDFN package to a pad connected to the PCB ground plane by a matrix of vias. Connecting the exposed pad is not a substitute for connecting the ground pin. Always connect pin 5 on the TDFN pack- age to ground. Chip Information TRANSISTOR COUNT: 624 PROCESS: CMOS Single/Dual LVDS Line Receivers with “In-Path” Fail-Safe 8 _______________________________________________________________________________________ CHARGE-CURRENT LIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Cs 100pF RC 1M Ω RD 1500 Ω HIGH- VOLTAGE DC SOURCE DEVICE UNDER TEST Figure 4a. Human Body ESD Test Modules IP 100% 90% 36.8% tRL TIME tDL CURRENT WAVEFORM PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Ir 10% 0 0 AMPERES Figure 4b. Human Body Current Waveform |
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