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SC28C94 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. SC28C94
Description  Quad universal asynchronous receiver/transmitter QUART
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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Philips Semiconductors
Product specification
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
1998 Aug 19
5
PIN DESCRIPTION
MNEMONIC
TYPE
NAME AND FUNCTION
CEN
I
Chip Select: Active low input that, in conjunction with RDN or WRN, indicates that the host MPU is trying to
access a QUART register. CEN must be inactive when IACKN is asserted.
A5:0
I
Address Lines: These inputs select a 28C94 register to be read or written by the host MPU.
D7:0
I/O
8-bit Bidirectional Data Bus: Used by the host MPU to read and write 28C94 registers.
RDN
I
Read Strobe: Active low input. When this line is asserted simultaneously with CEN, the 28C94 places the
contents of the register selected by A5:0 on the D7:0 lines.
WRN
I
Write Strobe: Active low input. When this line is asserted simultaneously with CEN, the 28C94 writes the data
on D7:0 into the register selected by A5:0.
DACKN
O
Data ACKnowledge: Active low, open-drain output to the host MPU, which is asserted subsequent to a read or
write operation. For a read operation, assertion of DACKN indicates that register data is valid on D7:0. For a
write operation, it indicates that the data on D7:0 has been captured into the indicated register. This signal
corresponds to READYN on 80x86 processors and DTACKN on 680x0 processors.
IRQN
O
Interrupt Request: This active low open-drain output to the host MPU indicating that one or more of the
enabled UART interrupt sources has reached an interrupt value which exceeds that pre-programmed by host
software. The IRQN can be used directly as a 680x0 processor input; it must be inverted for use as an 80x86
interrupt input. This signal requires an external pull-up resistor.
IACKN
I
Interrupt ACKnowledge: Active low input indicates host MPU is acknowledging an interrupt requested. The
28C94 responds by placing an interrupt vector or interrupt vector modified on D7-D0 and asserting DACKN. This
signal updates the CIR register in the interrupt logic. CEN must be high during this cycle.
TDa-d
O
Transmit Data: Serial outputs from the four UARTs.
RDa-d
I
Receive Data: Serial inputs to the four UARTs/
I/O0a-d
I/O
Input/Output 0: A multi-use input or output signal for each UART. These pins can be used as general purpose
inputs, Clear to Send inputs, 1X or 16X Transmit Clock outputs or general purpose outputs. Change-of-state
detection is provided for these pins. I/O pins have approximately 1.5 Mohm pull–up device.
I/O1a-d
I/O
Input/Output 1: A multi-use input or output signal for each UART. These pins can be used as general purpose
or 1X or 16X transmit clock inputs, or general purpose 1X or 16X receive clock outputs. Change-of-state
detection is provided for these pins. In addition, I/O1a and I/O1c can be used as Counter/Timer inputs and I/O1b
and I/O1d can be used as Counter/Timer outputs. I/O pins have approximately 1.5 Mohm pull–up device.
I/O2a-d
I/O
Input/Output 2: A multi-use input or output signal for each UART. These pins can be used as general purpose
inputs, 1X or 16X receive clock inputs, general purpose outputs, RTS output or 1X or 16X receive clock outputs.
I/O pins have approximately 1.5 Mohm pull–up device.
I/O3a-d
I/O
Input/Output 3: A multi-use input or output signal for each UART. These pins can be used as general purpose
inputs, 1X or 16X transmit clock inputs, general purpose outputs, or 1X or 16X transmit clock outputs. I/O pins
have approximately 1.5 Mohm pull–up device.
RESET
I
Master Reset: Active high reset for the 28C94 logic. Must be asserted at power-up, may be asserted at other
times that the system is to be reset and restarted. OSC set to divide by 1, MR pointer set to 1, DACKN enabled,
I/O pins to input. Registers reset: MR0, OPR, CIR. IRQN, DTACKN, IVR Interrupt Vector, Power Down, Test
registers, FIFO pointers, Baud rate generator, Error Status, Watch Dog Timers, Change of State detectors,
counter/timer to timer, Transmitter and Receiver controllers and all interrupt bits. If reset pin is not used, then
first chip access should be to celar ‘power-down’ mode.
X1/CLK
I
Crystal 1 or Communication Clock: This pin is normally connected to one side of a 3.6864MHz or a
7.3728MHz crystal, or can be connected to an external clock up to 8MHz.
X2
O
Crystal 2: If a crystal is used, this pin should be connected to its other terminal. If an external clock is applied to
X1, this pin should be left unconnected.
VCC, VSS
Power and grounds: respectively.
COUNTER/TIMER
I/O PORT CONTROL
UARTS A/B
INTERRUPT CONTROL
BLOCK B
UARTS C/D
I/O CONTROL
I/O PORT CONTROL
A0-A5
D (7:0)
DTACKN
IACKN
BAUD
RATE
GENERATOR
BUS
INTERFACE
BLOCK A
SD00161
Figure 4. Channel Architecture




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