Philips Semiconductors

Product specification

SC26C198 SC68C198

SC26L198 SC68L198

Octal UART with TTL compatibility at 3.3V

and 5V supply voltages

1995 May 1

339

Pin Description

MNEMONIC

TYPE

DESCRIPTION

SClk

I

Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater

than twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.

CEN

I

Chip select: Active low. When asserted, allows I/O access to OCTART registers by host CPU. W_RN signal

indicates direction. (Must not be active in IACKN cycle)

A(7:0)

I

Address lines (A[6] is NOT used. See ”Host Interface” )

D(7:0)

I/O

8–bit bi–directional data bus. Carries command and status information between 26C198 and the host CPU.

Used to convey parallel data for serial I/O between the host CPU and the 26C198

W_RN

I

Write Read not control: When high indicates that the host CPU will write to a 26C198 register or transmit FIFO.

When low, indicates a read cycle. 0 = Read; 1 = Write

DACKN

O

Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.

Open drain.

IRQN

O

Interrupt Request: Active low. When asserted, indicates that the 26C198 requires service for pending

interrupt(s). Open drain.

IACKN

I

Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt

acknowledge cycle. (Do not use CEN in an IACKN cycle)

TD(a–h)

O

Transmit Data: Serial outputs from the 8 UARTs.

RD(a–h)

I

Receive Data: Serial inputs to the 8 UARTs

I/O0(a–d)

I/O

Input/Output 0: Multi–use input or output pin for the UART.

I/O1(a–d)

I/O

Input/Output 1: Multi–use input or output pin for the UART.

I/O2(a–d)

I/O

Input/Output 2: Multi–use input or output pin for the UART.

I/O3(a–d)

I/O

Input/Output 3: Multi–use input or output pin for the UART.

I

Global general purpose inputs, available to any/all channels.

O

Global general purpose outputs, available from any channel.

RESETN

I

Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and

restart the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK.

X1/CCLK

I

Crystal 1 or Communication Clock: This pin may be connected to one side of a 2–8 MHz crystal. It may

alternatively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz

X2

O

Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin

must be left unconnected.

Power Supplies

I

16 pins total 8 pins for Vss, 8 pins for Vcc

NOTE: Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf.) These edges may move as fast as 1 to 3 ns

fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See

previous note on Sclk noise under pin assignments.

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

Operating ambient temperature range

See Note 3

°C

Storage temperature range

-65 to +150

°C

-0.5 to +7.0

V

Voltage from any pin to GND

V

PD5

1.2

W

PD3

0.5

W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is

not implied.