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SAA7188AWP Datasheet(PDF) 4 Page - NXP Semiconductors

Part # SAA7188AWP
Description  Digital Video Encoder DENC2-M
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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1996 Jul 08
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2-M)
SAA7188A
PINNING
SYMBOL
PIN
DESCRIPTION
VSSD1
1
digital ground 1
DP4
2
Upper 4 bits of the Data Port. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the parallel
MPU interface. If it is LOW, they are the UV lines of the Video Port.
DP5
3
DP6
4
DP7
5
RCV1
6
Raster Control 1 for Video port. Depending on the synchronization mode, this pin
receives/provides a VS/FS/FSEQ signal.
RCV2
7
Raster Control 2 for Video port. Depending on the synchronization mode, this pin
receives/provides an HS/HREF/CBL signal.
VSSD2
8
digital ground 2
VP0
9
Video Port. This is an input for CCIR 656 compatible, multiplexed video data. If the 16-bit
DIG-TV2 format is used, this is the Y data.
VP1
10
VP2
11
VP3
12
VP4
13
VP5
14
VP6
15
VP7
16
VDDD1
17
digital supply voltage 1
SEL_ED
18
Select Encoder Data. Selects data either from MPEG port or from video port as encoder input.
VSSD3
19
digital ground 3
MP7
20
MPEG Port. It is an input for CCIR 656 style multiplexed YUV data.
MP6
21
MP5
22
MP4
23
MP3
24
MP2
25
MP1
26
MP0
27
VSSD4
28
digital ground 4
RCM1
29
Raster Control 1 for MPEG port. This pin provides a VS/FS/FSEQ signal.
RCM2
30
Raster Control 2 for MPEG port. This pin provides an HS pulse for the MPEG decoder.
KEY
31
Key signal for OSD. It is active HIGH.
OSD0
32
On-Screen Display data. This is the index for the internal OSD look-up table.
OSD1
33
OSD2
34
VSSD5
35
digital ground 5
CDIR
36
Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC
and CREF are generated by the internal crystal oscillator.
VDDD2
37
digital supply voltage 2


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