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SAA7157T Datasheet(PDF) 4 Page - NXP Semiconductors |
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SAA7157T Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 12 page May 1992 4 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 CREF output TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency. Power-on reset Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied to reset other circuits of this digital TV system. The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH. PINNING Note 1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency. SYMBOL PIN DESCRIPTION MS 1 mode select input (LOW = PLL mode) CE 2 chip enable /reset (HIGH = outputs enabled) PORD 3 power-on reset delay, dependent on external capacitor VSSA 4 analog ground (0 V) VDDA 5 analog supply voltage ( +5 V) VSSD1 6 digital ground 1 (0 V) LL1.5A 7 line-locked clock output signal 1.5A (4 times fLFCO) VDDD1 8 digital supply voltage 1 ( +5 V) VSSD2 9 digital ground 2 (0 V) LL1.5B 10 line-locked clock output signal 1.5B (4 times fLFCO) LFCO 11 line-locked frequency control input signal 1 RESN 12 reset output (active-LOW, Fig.4) VSSD3 13 digital ground 3 (0 V) LL3A 14 line-locked clock output signal 3A (2 times fLFCO) CREF 15 clock reference output, qualifier signal (2 times fLFCO) LFCOSEL 16 LFCO source select (LOW = LFCO selected) (1) VDDD2 17 digital supply voltage 2 ( +5 V) VSSD4 18 digital ground 4 (0 V) LFCO2 19 line-locked frequency control input signal 2(1) LL3B 20 line-locked clock output signal 3B (2 times fLFCO) |
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