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SAA7128H Datasheet(PDF) 32 Page - NXP Semiconductors |
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SAA7128H Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 56 page  2000 Mar 08 32 Philips Semiconductors Product specification Digital video encoder SAA7128H; SAA7129H Table 56 Selection of luminance path delay Table 57 Selection of field length control Table 58 Subaddress 6FH Table 59 Selection of line 21 encoding Table 60 Subaddress 70H LDEL1 LDEL0 LUMINANCE PATH DELAY 0 0 no luminance delay; default value after reset 0 1 1 LLC luminance delay 1 0 2 LLC luminance delay 1 1 3 LLC luminance delay FLC1 FLC0 DESCRIPTION 0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default value after reset 0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz 1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz BIT SYMBOL DESCRIPTION 7 CCEN1 These 2 bits enable individual line 21 encoding; see Table 59. 6 CCEN0 5 TTXEN 0 = disables teletext insertion; default state after reset 1 = enables teletext insertion 4 SCCLN4 These 5 bits select the actual line where closed caption or extended data are encoded. 3 SCCLN3 line = (SCCLN[4:0] + 4) for M-systems line = (SCCLN[4:0] + 1) for other systems 2 SCCLN2 1 SCCLN1 0 SCCLN0 CCEN1 CCEN0 LINE 21 ENCODING 0 0 line 21 encoding off; default value after reset 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields BIT SYMBOL DESCRIPTION 7 to 0 RCV2S[7:0] These are the 8 LSBs of the 11-bit code that determines the start of the output signal on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H (see Table 62). Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading sync slope at CVBS output coincides with leading slope of RCV2 out at RCV2S = 49H. |
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