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SAA7118 Datasheet(PDF) 11 Page - NXP Semiconductors |
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SAA7118 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 169 page  2001 May 30 11 Philips Semiconductors Preliminary specification Multistandard video decoder with adaptive comb filter and component video input SAA7118 Notes 1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain. 2. In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. 3. For board design without boundary scan implementation connect the TRST pin to ground. 4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 5. Pin strapping is done by connecting the pin to the supply via a 3.3 k Ω resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). XPD3 134 B9 I/O MSB − 4 of expansion port data XPD2 135 A9 I/O MSB − 5 of expansion port data VDDD11 136 M8 P digital supply voltage 11 (peripheral cells) VSSD11 137 L8 P digital ground 11 (peripheral cells) XPD1 138 B8 I/O MSB − 6 of expansion port data XPD0 139 A8 I/O LSB of expansion port data XRV 140 D8 I/O vertical reference I/O expansion port XRH 141 C7 I/O horizontal reference I/O expansion port VDDD12 142 M9 P digital supply voltage 12 (core) XCLK 143 A7 I/O clock I/O expansion port XDQ 144 B7 I/O data qualifier for expansion port VSSD12 145 L9 P digital ground 12 (core) XRDY 146 A6 O task flag or ready signal from scaler, controlled by XRQT TRST 147 C6 I/pu test reset input (active LOW), for boundary scan test (with internal pull-up); notes 2, 3 and 4 TCK 148 B6 I/pu test clock for boundary scan test; note 2 TMS 149 D6 I/pu test mode select input for boundary scan test or scan test; note 2 TDO 150 A5 O test data output for boundary scan test; note 2 VDDD13 151 M11 P digital supply voltage 13 (peripheral cells) TDI 152 B5 I/pu test data input for boundary scan test; note 2 VSSD13 153 L11 P digital ground 13 (peripheral cells) VSS(xtal) 154 A4 P ground for crystal oscillator XTALI 155 B4 I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection of external oscillator with TTL compatible square wave clock signal XTALO 156 A3 O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL clock input of XTALI is used VDD(xtal) 157 B3 P supply voltage for crystal oscillator XTOUT 158 A2 O crystal oscillator output signal; auxiliary signal DNC9 159 C3 NC do not connect, reserved for future extensions and for testing DNC10 160 C4 NC do not connect, reserved for future extensions and for testing SYMBOL PIN TYPE(1) DESCRIPTION QFP160 BGA156 |
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