Electronic Components Datasheet Search |
|
SAA6588T Datasheet(PDF) 10 Page - NXP Semiconductors |
|
SAA6588T Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 28 page 1997 Sep 01 10 Philips Semiconductors Product specification RDS/RBDS pre-processor SAA6588 • One (MPX) as well as two (left and right) AF channel application is possible and requires only one pin • Unwanted crosstalk is avoided if two AF channel application is chosen • Matching the input sensitivity is possible by external resistors. For combined application (RDS and AMS) variations of the switching threshold level as well as the minimum time for pause detection are possible via I2C-bus control. The level can be adjusted in four steps of 4 dB by the control bits PL0 and PL1, see Table 8 (for 1 channel: R=5k Ω; for 2 channels: R = 10 kΩ). The corresponding values of FM deviation are calculated for stereo decoders with an output voltage of 270 mV at 22.5 kHz deviation. The minimum time for detecting a pause can be adjusted by the control bits SOSC, PTF0 and PTF1, see Table 9. The minimum time for detecting ‘no pause’ is fixed to 5 ms to avoid interruptions of a pause by a short pulse. The output signal of the pause detector is a digital switching signal (active LOW). It is directly available via the output pin PSWN. A detected pause may initiate an AF search if required (FM mode). Oscillator and clock For good performance of the band-pass and demodulator stages, the pre-processor requires a crystal oscillator with a frequency of n × 4.332 MHz. The pre-processor can be operated with one of four different oscillator frequencies (n = 1 to 4). The 17.328 MHz frequency (n = 4) is also UART interface compatible for 8051 based microcontrollers with a 9600 baud rate (frequency error = 4.5%), so that a radio set with microcontroller can run in this case with one crystal only. The pre-processor oscillator can drive the microcontroller or vice versa. According to the used oscillator frequency, the mode control bits PTF1, PTF0 and SOSC have to be set via the I2C-bus after every reset, see Section “Programming” The clock generator circuitry generates hereof the internally used 4.332 MHz system clock and further derived timing signals. Power supply and reset The pre-processor has separate power supply inputs for the digital and analog parts of the device. For the analog functions an additional reference voltage (1 ⁄2VDDA) is internally generated and available via the output pin Vref. The I2C-bus interface requires a defined reset condition. The pre-processor generates a reset signal: • After the supply voltage VDDD is switched on • At a supply voltage-drop • If the oscillator frequency is lower than 400 Hz. This internal reset initializes the I2C-bus interface registers as well as the I2C-bus slave control and releases the data line SDA (SDA = HIGH) for input of control mode settings from the main controller. If the decoder detects a reset condition, the status information ‘reset detected’ (RSTD) is set and available via I2C-bus request. The RSTD flag is deactivated after the decoder status register was read by the I2C-bus. This status information is important to signal the main controller about a voltage-drop in the pre-processor IC. By default, the bits in the write registers (except bit SOSC) are set to the values in Table 11. If these values are the required values, no further initialization is necessary. Programming I2C-BUS SLAVE TRANSCEIVER For communication with the external main controller (master transceiver) the standard I2C-bus is used. The pre-processors I2C-bus interface acts as a slave transceiver with fast mode option, that allows a transfer bit rate up to 400 kbits/s but is also capable of operating at lower rates ( ≤100 kbits/s). The I2C-bus interface is connected to the external I2C-bus via the serial clock line SCL and the serial data line SDA. The clock line is supplied by the master and is only input for the slave transceiver. The data line is a serial 8-bit oriented bidirectional data transfer line, and acts as input for control mode settings from the main controller to the pre-processor, as output for requested RDS/RBDS data from the pre-processor to the main controller and acknowledge between pre-processor and main controller. The transfer of requested data to the main controller is synchronized via the additional data available output signal DAVN to avoid loss of RDS/RBDS data. The DAVN signal is activated if the pre-processor has provided new data information for the main controller (see Section “RDS/RBDS data output”) and can be used for the polling mode as well as for the interrupt mode of the main microcontroller. |
Similar Part No. - SAA6588T |
|
Similar Description - SAA6588T |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |