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SP6652 Datasheet(PDF) 8 Page - Sipex Corporation

Part # SP6652
Description  1A, High Efficiency, Fixed 1.4 MHz Current Mode PWM Buck Regulator
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Manufacturer  SIPEX [Sipex Corporation]
Direct Link  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP6652 Datasheet(HTML) 8 Page - Sipex Corporation

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8
May25-07 RevH
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
© 2007 Sipex Corporation
APPLICATIONS INFORMATION
VOUT
C3
10
µF
R
FBH
R
FBL
SYNC
SD
Cc
10nF
Rz
4k
4.7
µH
L1
R1
10
C2
1
µF
C1
10
µF
VIN
SP6652
1
2
3
4
5
10
9
8
7
6
PGND
SGND
FB
COMP
SD
LX
PVIN
SVIN
SYNC
MODE
VIN
Complete Application Circuit.
The SP6652 PWM buck regulator circuit
requires 3 capacitors: 10µF for the PVIN input,
1µF input bypass for the SVIN and 10µF
for the output are typically recommended.
For the input capacitor, a value even larger
than 10µF will help reduce input voltage
ripple for applications sensitive to ripple on
the battery voltage. See the Typical Per-
formance Characteristics section for wave-
forms on input and output ripple with 10µF
capacitors. All the capacitors should be
surface mount ceramic for low lead induc-
tance necessary at the 1.4MHz switching
frequency of the SP6652 and to obtain low
ESR. This also helps improve bypassing
on the input pin and ripple on the output.
Ceramic capacitors with X5R or X7R tem-
perature grade are recommended for most
applications. A selection of recommended
capacitors is included in Table 1. The 1µF
SVIN input capacitor should have a series
resistor of about 10Ω value connected
from the input to the SVIN pin to form an RC
low pass filter to remove high frequency
spikes present on the input switching pin
COMPONENT SELECTION
PVIN. This will keep the SP6652 internal
reference and other sensitive circuits noise
free and ensure better output regulation.
The GND returns for the PVIN capacitor and
the output capacitor should be connected
directly to the PGND pin, which should con-
nect to the thermal pad ground located un-
der the SP6652. The GND return for the
1µF SVIN capacitor should be connected to
the SGND pin, which should be connected
separately to the PGND pin to avoid adding
PGND noise to the SP6652 SGND pin. See
the Typical SP6652 Circuit Layout for de-
tails on the recommended layout.
Output Voltage Selection
To set the output voltage for the SP6652,
a pair of resistors, RF and RI are used as a
voltage divider between the output voltage
at the output capacitor and the FB pin and
GND, as shown in the typical application cir-
cuit. The recommended value for the RI re-
sistor is 100KΩ to 200KΩ to keep the quies-
cent current low, but not have the impedance
too high at the FB pin for good regulation.


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