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SP6330EK1-L-V-G-C Datasheet(PDF) 7 Page - Sipex Corporation |
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SP6330EK1-L-V-G-C Datasheet(HTML) 7 Page - Sipex Corporation |
7 / 13 page Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation 7 Figure 1: Functionality of a SP63XX family member with manual reset and watchdog capabilities but without WDOB output. • V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding thresholds)---> RSTB is de-asserted after reset timeout period (Trp). • MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately. • WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is asserted for a duration of reset timeout period (Trp). • One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB is asserted immediately. THEORY OF OPERATION V1 V2 V3 V4 Vth1 Vth2 Vth3=0.5V Vth4=0.5V MRIB WDI RSTB Trp Trp Twd Trp T<Twd T<Twd T<Twd T<Twd T<Twd |
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