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XRK39910ID-5 Datasheet(PDF) 5 Page - Exar Corporation |
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XRK39910ID-5 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 9 page XRK39910 5 REV. 1.0.0 3.3V LOW SKEW PLL CLOCK DRIVER NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outputs. See AC TEST LOADS. 4. For XRK39910-2 tSKEW is measured with CL = 0pF; for CL = 20pF, tSKEW = 0.35ns Max. 5. tDEV is the output-to-output skew between any two devices operating under the same conditions. 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits. 7. tPD is measured with CLKIN input rise and fall times (from 0.8V to 2V ) of 1ns. TABLE 9: SWITCHING CHARACTERISTICS OVER OPERATING RANGE SYMBOL PARAMETER XRK39910-2 XRK39910-5 XRK39910-7 UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX FREF CLKIN Frequency Range FSEL = LOW 15 35 15 35 15 35 MHz FSEL = MED 25 60 25 60 25 60 FSEL = HIGH 40 85 40 85 40 85 tRPWH CLKIN Pulse Width HIGH 3 3 3 ns tRPWL CLKIN Pulse Width LOW 3 3 3 ns tSKEW Output Skew (All Outputs) [1, 3, 4] 0.1 0.25 0.25 0.5 0.3 0.75 ns tDEV Device-to-Device Skew [1, 2, 5] 0.75 1.25 1.65 ns tPD CLKIN Input to FB_IN Propagation Delay [1, 7] -0.25 0 0.25 -0.5 0 0.5 -0.7 0 0.7 ns tODCV Output Duty Cycle Variation from 50% [1] -1.2 0 1.2 -1.2 0 1.2 -1.2 0 1.2 ns tORISE Output Rise Time [1] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tOFALL Output Fall Time [1] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tLOCK PLL Lock Time [1,6] 0.5 0.5 0.5 ms tJR Cycle-to-Cycle Output Jit- ter [1] RMS 25 25 25 ps Peak-to-Peak 200 200 200 |
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