When designing a high power switching regulator, it becomes desirable to reduce the internal clamp voltage in

order, to keep a reasonable level of power dissipation of R . Adjusting the internal clamp voltage is very simple,

S

as shown in Figure 11. The two external diodes compensate the internal diodes so you get a constant clamp

voltage over temperature. Avoid too much reduction of the I

clamp voltage, or you will get noise pickup and

pk(max)

erratic results.

A narrow spike on the leading edge of the current waveform often occurs and can cause the power supply

instability when the output load is light. This spike is caused by power transformer interwinding capacitance and

output rectifier recovery time. You can eliminate this problem by adding an RC filter on the Current Sense Input,

with a time constant similar to the spike's duration; see Figure 16.

Undervoltage Lockout

Two UVLO comparators in GM384XA series assure that the chips are fully functional before the output stage is

enabled. The positive power supply terminal (V

) and the reference output (V ) have separate comparators.

CC

ref

Each has built-in hysteresis to prevent erratic output behavior as their thresholds are reached. The V

CC

comparator's upper and lower thresholds are 16 V/10 V for GM3842A and GM3844A, and 8.4V/7.6V for

GM3843A and GM3845A.

The V

comparator's upper and lower thresholds are 3.6V/3.4 V. The large hysteresis and low startup current of

ref

the GM3842A and GM3844A makes them ideal

for off-line converter applications where efficient bootstrap

startup is required.

GM3843A and GM3845A are intended for lower voltage DC-to-DC converter applications. A 36 V zener is

connected as a shunt regulator from V

to ground. Its purpose is to protect the IC from excessive voltage that

CC

can occur during system startup. The minimum operating voltage for GM3842A

and GM3844A is 11V; for

GM3843A and GM3845A it is 8.2V.

Output

GM384XA series has a single totem pole output stage that was designed for direct drive of power MOSFETs. It

provides up to ±1.0 A peak drive current and has a typical rise/ fall time of 50 ns with a 1.0 nF load. Additional

internal circuitry keeps the output in a sinking mode whenever a UVLO is active. This eliminates the need for an

external pull-down resistor.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at T = 25°C on the GM384XA series. Its primary

J

purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection

and it can provide more than 20mA for powering additional control system circuitry.

Design Considerations

Do not make your converter to use wire-wrap or plug-in prototype boards. High-frequency circuit layout

techniques must be observed to prevent pulsewidth jitter. This is usually caused by excessive noise pick-up

imposed on the Current Sense or Voltage Feedback inputs. You can improve noice immunity by lowering circuit

impedances at these points. The PCB layout should have a ground plane with low-current signal and high-

current switch and output grounds returning on separate paths to the input filter capacitor. Ceramic bypass

capacitors (0.1 µF) connected directly to V

, V , and V

may be required, depending upon circuit layout, to

CC

C

ref

provide a low impedance path for filtering high frequency noise. All high-current loops should be as short as

possible and use heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the

converter output voltage divider should be placed as close as possible to the GM384XA, and as far as possible

from the power switch and other noise- generating components.

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