XR68C192 datasheet(9/33 Pages) EXAR

Part #	XR68C192

Description	DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

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Manufacturer	EXAR [Exar Corporation]

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XR68C92/192

9

Rev. 1.33

and is controlled in a similar way by the channel B

registers.

OP2 - OP7:

The other outputs (OP2 - OP7) are configured via the

OPCR. Please see the description under the OPCR

register for the details.

CRYSTAL INPUTS (XTAL1 & XTAL2)

If a crystal is used, it is connected between XTAL1 and

XTAL2, in which case a capacitor of approximately 22

to 47 pF should be connected from each of these pins

to ground (see Figure 1). If an external CMOS-level

clock is used, the pin XTAL2 must be left open.

RESET

The XR68C92/192 can be reset by asserting the

-RESET signal or by programming the appropriate

internal registers. A hardware reset (assertion of

-RESET) clears the following registers:

• Status Registers A and B (SRA and SRB)

• Interrupt Mask Register (IMR)

• Interrupt Status Register (ISR)

• Output Port Configuration Register (OPCR)

RESET also performs the following operations:

• Initializes the interrupt vector register (IVR) to 0x0F.

• Places the outputs OP0 through OP7 in the high

state

• Places the counter/timer in counter mode

• Places channels A and B in the inactive state with the

transmitter serial-data outputs (TXA and TXB) in the

mark (high) state.

Reset commands can be programmed through the

command registers to reset the receiver, transmitter,

error status, or break-change interrupts for each chan-

nel.

TRANSMITTER

The transmitter converts the parallel data from the

CPU to a serial bit stream on the transmitter output pin

(TXA, TXB). It automatically sends a start bit followed

by the programmed number of data bits, an optional

parity bit, and the programmed number of stop bits.

The least-significant bit is sent first. Data is shifted out

the transmit serial data output pin (TXA, TXB) on the

falling edge of the programmed clock source (XTAL1,

IP3 or IP5: see CSR bits 3:0). After the transmission of

the stop bits, and a new character is not available in the

transmit FIFO, the transmitter serial data output (TXA,

TXB) remains high. Transmission resumes when the

CPU loads a new character into the transmit FIFO. If

the transmitter receives a disable command (CRA,

CRB bits 3:2), it will continue operating until the char-

acter in the transmit shift register is completely sent

out. Other characters in the FIFO are neither sent nor

discarded, but will be sent when the transmitter is re-

enabled.

TX RTS Control: Users can program the transmitter to

automatically negate the request-to-send (RTS) out-

put (alternate function of OP0 and OP1 for channels A

and B respectively) on completion of a message trans-

mission (using MR2A, MR2B bit-5). If the transmitter is

programmed to operate with RTS control, the RTS

output must be manually asserted before each mes-

sage is transmitted. Also, the transmitter needs to be

disabled after all the required data are loaded into the

FIFO. Then, the RTS output will be automatically

negated when the transmit-shift register and the TX

FIFO are both empty. In automatic RTS mode, no more

characters can be written to the FIFO after the trans-

mitter is disabled.

If auto clear-to-send (CTS) control is enabled (using

MR2A, MR2B bit-4), the CTS input (alternate function

of IP0 and IP1 for channels A and B respectively) must

be asserted (low) in order for the character to be

transmitted. If it gets negated (high) in the middle of a

transmission, the character in the shift register is

transmitted and the transmit data output (TXA, TXB)

then remains in the marking state until CTSA, CTSB

gets asserted again.

The transmitter can also be forced to send a continu-

ous low (space) condition by issuing the start-break

command (see CRA, CRB bits 7:4). The state of CTS

is ignored by the transmitter when it is set to send a

break.

NOTE: The terms assertion and negation will be used

extensively to avoid confusion when dealing with a

mixture of “active low” and “active high” signals. The

term assert or assertion indicates that a signal is active

or true, independent of whether that level is repre-

sented by a high or low voltage. The term negate or

negation indicates that a signal is inactive or false.

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