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SAA2022 Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA2022 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 52 page  Philips Semiconductors Product specification Tape formatting and error correction for the DCC system SAA2022 February 1994 8 The SAA2022 provides the following functions: In Playback Modes • Tape channel data and clock recovery • 10 to 8 demodulation • Data placement in DRAM • C1 and C2 error correction decoding • I2S-interfacing to SB-I2S-bus • Interfacing to microcontroller for SYSINFO and AUX data • Capstan control for tape deck. In Record Modes • I2S-interfacing to SB-I2S-bus • C1 and C2 error correction encoding • Formatting for tape transfer • 8 to 10 modulation • Interfacing to microcontroller for SYSINFO and AUX data • Capstan control for tape deck, programmable by microcontroller. Operational Modes The 3 basic modes of operation are: • DPAP - Main data (audio) and SYSINFO play, AUX play • DRAR - Main data (audio) and SYSINFO record, AUX record • DPAR - Main data (audio) and SYSINFO play, AUX record. Hardware Interfacing RESET This is an active HIGH input signal which resets the SAA2022 and brings it into its default mode, DPAP. This should be connected to the system reset, which can be driven by the microcontroller. The duration of the reset pulse should be at least 15 µs. This pin has an internal pull-down resistor of between 20 k Ω and 125 kΩ. PWRDWN This pin is an active HIGH signal which places the SAA2022 in a “SLEEP” mode. When the SAA2022 is in “SLEEP” mode and the CLK24 is either held HIGH or held LOW, there is no activity in the device, thus resulting in no EMI and a low power dissipation (typically <10% of operational dissipation). This pin should be connected to the DCC power-down signal, which can be driven by the system microcontroller. To enter the “SLEEP” mode the SAA2022 should reset and hold reset. After a delay of at least 15 µs the PWRDWN pin should be brought HIGH after which the state of the reset pin is “don’t care”. The power dissipation is reduced further when the CLK24 input signal stops. When recovering from “SLEEP” mode the PWRDWN pin should be driven LOW and the chip reset with a pulse of at least 15 µs duration. CLK24 This is the 24.576 MHz clock input and should be connected directly to the SAA2002 CLK24 pin. Connections to SAA2032 TCH0 TO TCH7 AND TAUX These lines are the equalized and clipped (to V DD) tape channel inputs and should be connected to the SAA2032 pins TCH0 to TCH7 and TAUX. Sub-band I2S-bus Connections The timing for the SB-I2S-interface is given in Figs 4 to 9. |
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