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PRELIMINARY XR19L400 3 REV. P1.0.0 SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER PIN DESCRIPTIONS Pin Descriptions NAME 40-QFN PIN# TYPE DESCRIPTION DATA BUS INTERFACE (CMOS/TTL Voltage Levels) A2 A1 A0 39 40 1 I Address bus lines [2:0]. These 3 address lines select one of the internal registers in the UART during a data bus transaction. D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 I/O Data bus lines [7:0] (bidirectional). IOR# (NC) 15 I When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used. IOW# (R/W#) 14 I When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe (active LOW). The falling edge instigates the internal write cycle and the rising edge trans- fers the data byte on the data bus to an internal register pointed by the address lines. When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read (HIGH) and write (LOW) signal. CSA# (CS#) 10 I When I/M# pin is HIGH, this input is chip select A (active low) to enable channel A in the device. When I/M# pin is LOW, this input becomes the chip select (active low) for the Motorola bus interface. INTA (IRQ#) 38 O (OD) When I/M# pin is HIGH, it selects Intel bus interface and this output become the active HIGH device interrupt output for channel A. This output is enabled through the software set- ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three state mode when MCR[3] is set to a logic 0. See MCR[3]. When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active LOW, open-drain interrupt output for both channels. An external pull-up resistor is required for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt. SERIAL I/O INTERFACE (RS-485/RS-485 Voltage Levels) TX+ TX- 32 30 O Differential UART Transmit Data. RX+ RX- 28 27 I Differential UART Receive Data. ANCILLARY SIGNALS (CMOS/TTL Voltage Levels) HALF/ FULL# 34 I When HALF/FULL# is HIGH, half-duplex mode is enabled. When HALF/FULL# is LOW, full-duplex mode is enabled. XTAL1 12 I Crystal or external clock input. |
