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XR16L580IM Datasheet(PDF) 8 Page - Exar Corporation |
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XR16L580IM Datasheet(HTML) 8 Page - Exar Corporation |
8 / 52 page XR16L580 8 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The L580 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. XR16L580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS VCC VCC A0 A1 A2 UART_CS# IOR# IOW# D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CS# D0 D1 D2 D3 D4 D5 D6 D7 IOR# IOW# UART_INT INT Serial Interface of RS-232 or RS-422 Intel Data Bus Interconnections GND UART_RESET RESET 16/68# RI# CD# DSR# CTS# RTS# DTR# RX TX PwrSave VCC VCC A0 A1 A2 UART_CS# R/W# D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CS# D0 D1 D2 D3 D4 D5 D6 D7 IOR# IOW# UART_IRQ# INT Serial Interface of RS-232 or RS-422 Motorola Data Bus Interconnections GND UART_RESET# RESET RI# CD# DSR# CTS# RTS# DTR# RX TX PwrSave VCC 16/68# |
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