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XR16L580IL Datasheet(PDF) 11 Page - Exar Corporation |
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XR16L580IL Datasheet(HTML) 11 Page - Exar Corporation |
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11 / 52 page  XR16L580 11 REV. 1.4.1 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com. 2.9 Programmable Baud Rate Generator The L580 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input crystal or external clock by a factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor (via DLL and DLM registers) between 1 and (216 -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power up. Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation. FIGURE 6. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE FIGURE 7. BAUD RATE GENERATOR AND PRESCALER divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16) 2K XTA L 1 XTA L 2 R1 VC C E x te rnal C loc k vcc gnd XTAL1 XTAL2 Crystal Osc/ Buffer MCR Bit-7=0 (default) MCR Bit-7=1 DLL and DLM Registers Prescaler Divide by 1 Prescaler Divide by 4 16X Sampling Rate Clock to Transmitter Baud Rate Generator Logic |
Similar Part No. - XR16L580IL |
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Similar Description - XR16L580IL |
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