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XR19L200IL32 Datasheet(PDF) 11 Page - Exar Corporation |
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XR19L200IL32 Datasheet(HTML) 11 Page - Exar Corporation |
11 / 40 page XR19L200 11 REV. 1.0.1 SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. 2.11.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. 2.12 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled (See Table 10), the L200 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the L200 will halt transmission (TX) as soon as the current character has completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output pin will be activated. Following a suspension due to a match of the Xoff character, the L200 will monitor the receive data stream for a match to the Xon-1,2 character. If a match is found, the L200 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/ Xoff characters (See Table 10) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the L200 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the L200 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L200 sends the Xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after the receive FIFO crosses the programmed trigger level. To clear this condition, the L200 will transmit the programmed Xon character(s) as soon as receive FIFO is less than one trigger level below the programmed trigger level (see Table 8). The table below describes this. FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE Receive Data Shift Register (RSR) Receive Data Byte and Errors RHR Interrupt (ISR bit-2) Receive Data Holding Register (RHR) RXFIFO1 16X Clock Receive Data Characters Data Bit Validation Error Tags in LSR bits 4:2 |
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