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XR16V2552IL32 Datasheet(PDF) 9 Page - Exar Corporation |
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XR16V2552IL32 Datasheet(HTML) 9 Page - Exar Corporation |
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9 / 48 page  XR16V2552 9 REV. 1.0.2 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 2.8 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 17 through 22. 2.9 Crystal Oscillator or External Clock Input The V2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.10, Programmable Baud Rate Generator with Fractional Divisor” on page 10.” FIGURE 4. TYPICAL CRYSTAL CONNECTIONS TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER AUTO RS485 MODE FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INTA/B Pin NO LOW = a byte in THR HIGH = THR empty LOW = FIFO above trigger level HIGH = FIFO below trigger level or FIFO empty INTA/B Pin YES LOW = a byte in THR HIGH = transmitter empty LOW = FIFO above trigger level HIGH = FIFO below trigger level or transmitter empty TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INTA/B Pin LOW = no data HIGH = 1 byte LOW = FIFO below trigger level HIGH = FIFO above trigger level C1 22-47pF C2 22-47pF Y1 1.8432 MHz to 24 MHz R1 0-120 (Optional) R2 500K - 1M XTAL1 XTAL2 |
Similar Part No. - XR16V2552IL32 |
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Similar Description - XR16V2552IL32 |
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