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XR16L570IL24 Datasheet(PDF) 3 Page - Exar Corporation |
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XR16L570IL24 Datasheet(HTML) 3 Page - Exar Corporation |
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3 / 47 page  XR16L570 3 REV. 1.0.1 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE PIN DESCRIPTIONS Pin Descriptions NAME 24-QFN PIN# 32-QFN PIN# TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 12 13 14 17 18 19 I Address data lines [2:0]. These 3 address lines select one of the internal registers in the UART during a data bus transaction. D7 D6 D5 D4 D3 D2 D1 D0 3 2 1 24 23 22 21 20 5 4 3 1 32 31 30 29 I/O Data bus lines [7:0] (bidirectional). IOR# 11 14 I This input is the read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. IOW# 9 12 I This input is the write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal regis- ter pointed by the address lines. CS# 6 8 I This input is chip select (active low) to enable the device. INT 15 20 O This output is the active high device interrupt output. The output state is defined by the user through the software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See MCR[3]. MODEM OR SERIAL I/O INTERFACE TX 5 7 O UART Transmit Data or infrared encoder data. Standard transmit and receive inter- face is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it unconnected. RX 4 6 I UART Receive Data or infrared receive data. Normal receive data input must idle at logic 1 condition. The infrared receiver idles at logic 0. RTS# 16 21 O UART Request-to-Send (active low) or general purpose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6]. CTS# 18 24 I UART Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to VCC when not used. DTR# - 22 O UART Data-Terminal-Ready (active low) or general purpose output. This pin is not available in the 24-QFN package. DSR# - 25 I UART Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. This pin is not available in the 24-QFN package. |
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