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XR16C2550 Datasheet(PDF) 3 Page - Exar Corporation |
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XR16C2550 Datasheet(HTML) 3 Page - Exar Corporation |
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3 / 37 page  XR16C2550 3 REV. 1.0.2 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PIN DESCRIPTIONS Pin Description NAME 40-PDIP PIN # 44-PLCC PIN # 48-TQFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 26 27 28 29 30 31 26 27 28 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transac- tion. D7 D6 D5 D4 D3 D2 D1 D0 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 3 2 1 48 47 46 45 44 IO Data bus lines [7:0] (bidirectional). IOR# 21 24 19 I Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. IOW# 18 20 15 I Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. CSA# 14 16 10 I UART channel A select (active low) to enable UART channel A in the device for data bus operation. CSB# 15 17 11 I UART channel B select (active low) to enable UART channel B in the device for data bus operation. INTA 30 33 30 O UART channel A Interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0 (default). See MCR[3]. INTB 29 32 29 O UART channel B Interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1 when MCR[3] is set to a logic 0 (default). See MCR[3]. TXRDYA# - 1 43 O UART channel A Transmitter Ready (active low). The output pro- vides the TX FIFO/THR status for transmit channel A. See Table 2. If it is not used, leave it unconnected. RXRDYA# - 34 31 O UART channel A Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel A. See Table 2. If it is not used, leave it unconnected. TXRDYB# - 12 6 O UART channel B Transmitter Ready (active low). The output pro- vides the TX FIFO/THR status for transmit channel B. See Table 2. If it is not used, leave it unconnected. |
Similar Part No. - XR16C2550_07 |
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Similar Description - XR16C2550_07 |
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