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C1206N43931G4C Datasheet(PDF) 4 Page - Kemet Corporation |
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C1206N43931G4C Datasheet(HTML) 4 Page - Kemet Corporation |
4 / 30 page ©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300 CERAMIC CHIP CAPACITORS the vector summation of the capacitive reactance, the inductive reactance, and the ESR, as illustrated in Figure 2. As frequency increases, the capacitive reac- tance decreases. However, the series inductance (L) shown in Figure 1 produces some inductive reactance, which increases with frequency. At some frequency, the impedance ceases to be capacitive and becomes inductive. This point, at the bottom of the V-shaped impedance versus frequency curves, is the self-reso- nant frequency. At the self-resonant frequency, the reactance is zero, and the impedance consists of the ESR only. At high frequency more detailed models apply - See KEMET SPICE models for such instances. Typical impedance versus frequency curves for KEMET multilayer ceramic capacitors are shown in Figures 4, 5, 6 and 7. ENVIRONMENTAL AND PHYSICAL 13. Thermal Shock: EIA-198, Method 202, Condition B (5 cycles -55° to + 125°C). 14. Life Test: EIA-198, Method 201, 1000 hours at 200%* of rated voltage at 125°C. (Except 85°C for Z5U , Y5V & X5R). 15. Humidity Test: EIA-198, Method 206, ( Except 1000 hours,85°C, 85% RH, Rated Voltage). 16. Moisture Resistance: EIA-198, Method 204, Condition B (20 cycles with 50 volts applied. 17. Solderability: EIA-198, Method 301 (245°, 5 secs, Sn62 solder) 95% smooth solder on terminations. See page 14 for recommended profiles. 18. Resistance to Soldering Heat: EIA-198, Method 302, Condition B (260°C, 10 sec- onds) no leaching of nickel barrier. 19. Terminal Strength: EIA-198, Method 303, Condition D . RELIABILITY 20. A well constructed multilayer ceramic capacitor chip is extremely reliable and, for all practical purposes, has no wearout mechanism when used within the maximum voltage and temperature ratings. Most failures occur as a result of mechanical or thermal damage during mounting on the board, or during subsequent testing. Capacitor failure may also be induced by sustained operation at voltages that exceed the rated DC voltage, voltage spikes or transients that exceed the dielectric's voltage capability, sustained operation at temperatures above the maximum rated temperature, internal defects, or excessive temperature rise due to power dissipation. As with any practical device, multilayer ceramic capacitors also possess an inherent, although low, failure rate when operated within rated conditions. The primary failure mode is by short-circuit or low insu- lation resistance, resulting from cracks or from dielectric breakdown at a defect site. KEMET monitors reliability with a periodic sampling program for selected values. Results are available in our FIT (Failure in Time) report for commercial chips. 21. Storage and Handling: Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term stor- age. In addition, packaging materials will be degraded by high temperature – reels may soften or warp, and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40 degrees C, and maximum storage humidity not exceed 70% relative humidity. In addition, temperature fluctua- tions should be minimized to avoid condensation on the parts, and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solder- ability, chip stock should be used promptly, preferably within 1.5 years of receipt. MISAPPLICATION 22. Ceramic capacitors, like any other capacitors, may fail if they are misapplied. Some misapplications include mechanical damage, such as impact or excessive flex- ing of the circuit board. Others include severe mounting or rework cycles that may also introduce thermal shock. Still others include exposure to excessive voltage, cur- rent or temperature. If the dielectric layer of the capaci- tor is damaged by misapplication, the circuit may fail. The electrical energy of the circuit can be released as heat, which may damage the circuit board and other components as well. ADDITIONAL INFORMATION 23. Detailed application information can be found in KEMET Engineering Bulletins. F-2100 Surface Mount-Mounting Pad Dimensions and Considerations F-2102 Reflow Soldering Process F-2105 Wave Solder Process F-2103 Surface Mount Repair F-2110 Capacitance Monitoring while Flex Testing F-2111 Ceramic Chip Capacitors “Flex Cracks” - Understanding and Solutions For analysis of high frequency applications, KEMET has SPICE models of most chip capacitors. Models may be downloaded from KEMET’s website www.kemet.com. Additional information is also available - See your KEMET representative for details or post your questions to KEMET's homepage on the web http://www.kemet.com. *Note: 150% of rated voltage for selected high capacitance X5R values. Please contact factory. 70 See Table 4 on page 71 for limits. See Table 4 on page 71 for limits. See Table 4 on page 71 for limits. |
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