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© Andigilog, Inc. 2006
www.andigilog.com
August 2006 - 70A04010
aSC7511
35ms, allowing all SMBus devices to be reset. This follows
the SMBus 2.0 specification of 25-35ms.
When the aSC7511 detects an SMBus reset, it will prepare
to accept a new start sequence and resume
communication from a known state
S
0
Figure 2. Register Address Pointer Set
A7
A6
A5
A4
A3
A2
A1
A0
Start
0
SMBus Device Address Byte (4Ch)
Register Address Byte
1
1
1
0
0
S
A
A
ACK
from
aSC7511
ACK
from
aSC7511
9
1
9
1
SCL
SDA
0
Figure 3. Register Write
A7
A6
A5
A4
A3
A2
A1
A0
Start
0
SMBus Device Address Byte (4Ch)
Register Address Byte
1
1
1
0
0
R/W
S
A
A
ACK
from
aSC7511
ACK
from
aSC7511
SCL
SDA
0
1
9
1
9
Stop
by
Master
1
9
D7
D6
D5
D4
D3
D2
D1
D0
Register Data Byte
A
ACK
from
aSC7511
Stop
By
Master
SMBus Device Address Byte (4Ch)
ACK
from
aSC7511
NACK
from
Master
SCL
SDA
1
9
1
9
Stop
by
Master
Figure 5. Register Read When Read Address Already Set
D7
D6
D5
D4
D3
D2
D1
D0
Start
0
Register Data Byte
1
1
1
0
0
S
A
N
0 R/W
R/W
Figure 4. Register Read
1
0
0
1
1
0
0
1
Start
0
SMBus Alert Response Address Byte (0Ch)
aSC7511 SMBus Address
1
1
0
0
A
N
ACK
from
aSC7511
NACK
from
Master
SCL
SDA
0
1
9
1
9
Stop
by
Master
Figure 6. SMBus Alert Response
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Re-start
0
Register Data Byte
1
1
1
0
0
S
A
N
0 R/W
SMBus Device Address Byte (4Ch)
aSC7511
ACK
from
NACK
from
Master
Stop
by
Master
Register Address
Pointer Set
(Figure 2.)
without stop by Master
+
1
9
1
9