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MPC8555EPXAJF Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MPC8555EPXAJF Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
4 / 88 page MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4 4 Freescale Semiconductor Overview — Two full-duplex fast communications controllers (FCCs) that support the following protocols: – ATM protocol through two UTOPIA level 2 interfaces – IEEE802.3/Fast Ethernet (10/100) – HDLC – Totally transparent operation — Three full-duplex serial communications controllers (SCCs) support the following protocols: – High level/synchronous data link control (HDLC/SDLC) – LocalTalk (HDLC-based local area network protocol) – Universal asynchronous receiver transmitter (UART) – Synchronous UART (1x clock mode) – Binary synchronous communication (BISYNC) – Totally transparent operation – QMC support, providing 64 channels per SCC using only one physical TDM interface — Universal serial bus (USB) controller that is full/low-speed compliant (multiplexed on an SCC) – USB host mode – Supports USB slave mode — Serial peripheral interface (SPI) support for master or slave —I2C bus controller — Two serial management controllers (SMCs) supporting: – UART – Transparent – General-circuit interfaces (GCI) — Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM formats: – T1/CEPT lines –T3/E3 – Pulse code modulation (PCM) highway interface – ISDN primary rate – Freescale interchip digital link (IDL) – General circuit interface (GCI) — User-defined interfaces — Eight independent baud rate generators (BRGs) — Four general-purpose 16-bit timers or two 32-bit timers — General-purpose parallel ports—16 parallel I/O lines with interrupt capability • 256 Kbytes of on-chip memory — Can act as a 256-Kbyte level-2 cache — Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays |
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