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MPC8555EPXAPE Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC8555EPXAPE Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 88 page MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4 2 Freescale Semiconductor Overview 1 Overview The following section provides a high-level overview of the MPC8555E features. Figure 1 shows the major functional units within the MPC8555E. Figure 1. MPC8555E Block Diagram 1.1 Key Features The following lists an overview of the MPC8555E feature set. • Embedded e500 Book E-compatible core — High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture — Dual-issue superscalar, 7-stage pipeline design — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection — Lockable L1 caches—entire cache or on a per-line basis — Separate locking for instructions and data — Single-precision floating-point operations — Memory management unit especially designed for embedded applications — Enhanced hardware and software debug support — Dynamic power management — Performance monitor facility I2C Controller Local Bus Controller 64/32b PCI Controller 0/32b PCI Controller DMA Controller 10/100/1000 MAC 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs Serial DMA ROM I-Memory DPRAM RISC Engine Parallel I/O Baud Rate Generators Timers FCC FCC SCC/USB SMC SPI I2C MPHY MIIs/RMIIs TDMs I/Os CPM DDR SDRAM Controller CPM Controller Interrupt 256 Kbyte L2 Cache/ SRAM e500 Core 32-Kbyte L1 I Cache 32-Kbyte L1 D Cache Core Complex e500 Coherency Module OCeaN IRQs SDRAM DDR GPIO 32b Programmable Interrupt Controller UTOPIA Bus DUART SCC SMC SCC Security Engine |
Similar Part No. - MPC8555EPXAPE |
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Similar Description - MPC8555EPXAPE |
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