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MH32S72AVJA-6 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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MH32S72AVJA-6 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
1 / 56 page 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72AVJA-6 17.Mar.2000 MIT-DS-0376-0.2 MITSUBISHI LSIs Preliminary Spec. Some contents are subject to change without notice. MITSUBISHI ELECTRIC DESCRIPTION APPLICATION Main memoryor graphic memoryin computer systems 1 1pin 10pin 11pin 40pin 41pin 84pin 85pin 94pin 95pin 124pin 125pin 168pin The MH32S72AVJA is 33554432 - word x 72-bit Sy nchronous DRAM module. This consist of eighteen industry standard 32M x 4 Sy nchronous DRAMs in TSOP. The TSOP on a card edge dual in-line package prov ides any application where high densities and large of quantities memory are required. This is a socket-ty pe memory m odule ,suitable f or easy interchange or addition of module. FEATURES 5.4ns (CL = 4 at Latch mode) -6 Utilizes industry standard 32M X 4 Synchronous DRAMs in TSOP package , industrystandard Resistered buffer in TSSOP package,industry standard PLL in TSSOP package Single 3.3V +/- 0.3V supply Max.Clock frequency 133MHz Fully synchronous operation referenced to clock rising edge 4-bank operation controlled byBA0,BA1(Bank Address) /CAS latency-2/3(programmable,at buffer mode) LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst type- Sequential and interleave burst (programmable) Random column access Burst W rite / Single W rite(programmable) Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycles every 64ms Max. Frequency Access Time from CLK [component level] 133MHz Discrete IC and module design conform to PC133 specification. |
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