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MPC859 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MPC859 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 96 page  MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 5 Features • One serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus • One inter-integrated circuit (I2C) port — Supports master and slave modes — Multiple-master environment support • Time slot assigner (TSA) (MPC859DSL does not have TSA.) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — Allows dynamic changes — On MPC866P and MPC866T, can be internally connected to six serial channels (four SCCs and two SMCs); on MPC859P and MPC859T, can be connected to three serial channels (one SCC and two SMCs). • Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on MPC866/859 or MC68360 • PCMCIA interface — Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1) — Supports one or two PCMCIA sockets whether ESAR functionality is enabled — Eight memory or I/O windows supported • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data. — Supports conditions: = ≠ < > — Each watchpoint can generate a breakpoint internally • Normal high and normal low power modes to conserve power • 1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to Table 6 for a listing of the 5-V tolerant pins. • 357-pin plastic ball grid array (PBGA) package • Operation up to 133 MHz |
Similar Part No. - MPC859 |
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Similar Description - MPC859 |
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