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OXCB950 Datasheet(PDF) 8 Page - Oxford Semiconductor |
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OXCB950 Datasheet(HTML) 8 Page - Oxford Semiconductor |
8 / 67 page DS-0033 Sep 05 External-Free Release Page 8 OXCB950 OXFORD SEMICONDUCTOR LTD. 4 PIN DESCRIPTIONS Cardbus/PCI bus Pins Dir2 Name Description 1, 3, 4, 5, 8, 9, 10, 11, 16, 17, 18, 19, 22, 23, 24, 25, 52, 53, 54, 57, 58, 60, 61, 66, 69, 73, 74, 75, 77, 78, 79, 100 C/P_I/O AD[31:0] Multiplexed Address/Data bus. 67, 80, 99, 15 C/P_I C/BE[3:0]# Multiplexed Command/Byte enable. 88 CP_I CLK System clock 83 CP_I FRAME# Cycle Frame1. 93 CP_O DEVSEL# Device Select 84 CP_I IRDY# Initiator ready 85 CP_O TRDY# Target ready 95 CP_O STOP# Target Stop request 98 CP_I/O PAR Parity 72 CP_O SERR# System error 96 CP_I/O PERR# Parity error 68 CP_I IDSEL Initialisation device select For PCI applications this pin must be connected to the IDSEL pin on the PCI connector. For cardbus applications, there is no IDSEL signal, so this pin must be tied to Vdd (3.3v) via a pull-up on the board. (10K recommended). 86 CP_I RST# System reset 94 CP_OD INTA# /CINT# Interrupt Pin. For both cardbus and pci applications 59 CP_O CSYSCHG Power management event signal, for Cardbus applications This pin must be No-Connect (NC) for PCI applications. 51 CP_OD PME# Power management event signal, for PCI applications This pin must be No-Connect (NC) for cardbus applications. 32 I SLEW_RATE Slew rate control for cardbus/pci outputs For cardbus applications, this must be tied to Vdd on the board. For PCI applications, this must be tied to Gnd on the board. |
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