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MPC859P/859T/859DSL PowerQUICC™ FamilyTechnical Summary

MOTOROLA

Features

Features

1.1

Features

The following list summarizes the key MPC859P/859T/859DSL Family features:

•

Embedded MPC8xx core up to 133 MHz

•

Maximum frequency operation of the external bus is 66 MHz

— The 133MHz/100MHz core frequencies support 2:1 mode only

— The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes

•

Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32, 32-bit

general-purpose registers (GPRs)

— The core performs branch prediction with conditional prefetch, without conditional execution

— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).

– 16-Kbyte instruction cache (MPC859P) is four-way, set-associative with 256 sets;4-Kbyte

instruction cache (MPC859T and MPC859DSL) is two-way, set-associative with 128 sets.

– 8-Kbyte data cache (MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte data

cache (MPC859T and MPC859DSL) is two-way, set-associative with 128 sets.

– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)

cache blocks.

– Caches are physically addressed, implement a least recently used (LRU) replacement

algorithm, and are lockable on a cache block basis.

— MMUs with 32-entry TLB, fully associative instruction and data TLBs

— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address

spaces and 16 protection groups

•

The MPC859P/859T/859DSL Family provides enhanced ATM functionality as found on the

MPC866. The MPC859P/859T/859DSL adds major new features available in “enhanced SAR”

(ESAR) mode, including the following:

— Improved operation, administration and maintenance (OAM) support

— OAM performance monitoring (PM) support

— Multiple APC priority levels available to support a range of traffic pace requirements

— Port-to-port switching capability without the need for RAM-based microcode

— Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability

— Optional statistical cell counters per PHY

Table 1. MPC859T Family

Part

Cache

Ethernet

SCC

ATM Support

Instruction

Cache

Data Cache

10Base

T

10/100

MPC859P

16 Kbyte

8 Kbyte

1

1

1

Serial ATM and UTOPIA

Interface

MPC859T

4 Kbyte

4 Kbyte

1

1

1

Serial ATM and UTOPIA

Interface

MPC859DSL

4 Kbyte

4 Kbyte

1

1

1

Serial ATM and UTOPIA

Interface

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com