MOTOROLA

MPC859P/859T/859DSL PowerQUICC™ FamilyTechnical Summary

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Features

— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell

transmission time. (The earlier UTOPIA level 1 specification is also supported.)

— Multi-PHY support on the MPC859P and MPC859T (Four PHY Support on the MPC859DSL)

— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a

“split” bus

— AAL2/VBR functionality is ROM-resident

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Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

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32 address lines

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Memory controller (eight banks)

— Contains complete dynamic RAM (DRAM) controller

— Each bank can be a chip select or RAS to support a DRAM bank

— Up to 30 wait states programmable per memory bank

— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, flash EPROMs, and other memory

devices

— DRAM controller programmable to support most size and speed memory interfaces

— Four CAS lines, four WE lines, one OE line

— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)

— Variable block sizes (32 Kbyte–256 Mbyte)

— Selectable write protection

— On-chip bus arbitration logic

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General-purpose timers

— Four 16-bit timers or two 32-bit timers

— Gate mode can enable/disable counting

— Interrupt can be masked on reference match and event capture

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Fast Ethernet controller (FEC)

— Simultaneous MII (100Base-T) and UTOPIA operation when using the UTOPIA multiplexed

bus.

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System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE 1149.1 test access port (JTAG)

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Interrupts

— Seven external interrupt request (IRQ) lines

— 12 port pins with interrupt capability

— 20 internal interrupt sources

— Programmable priority between SCCs

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com