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MC33882VW Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc

Part # MC33882VW
Description  Six-Output Low-Side Switch with SPI and Parallel Input Control
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC33882VW Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
11
33882
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V
≤ V
DD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40°C ≤ TA ≤ 125°C unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (27)
tR
1.0
10
µs
Output Fall Time (27)
tF
1.0
10
µs
Output Turn-ON Delay Time (28)
tDLY(ON)
1.0
10
µs
Output Turn-OFF Delay Time (29)
tDLY(OFF)
1.0
10
µs
Output Short Fault Sense Time (30)
RLOAD = < 1.0 V
tSS
25
100
µs
Output Short Fault Refresh Time (31)
RLOAD = < 1.0 V
tREF
3.0
4.5
6.0
ms
Output OFF Open Load Sense Time (32)
tOS(OFF)
25
60
100
µs
Output ON Open Load Sense Time (33)
tOS(ON)
3.0
12
ms
Output Short Fault ON Duty Cycle (34)
SCDC
0.42
3.22
%
DIGITAL INTERFACE TIMING
SCLK Clock High Time (SCLK = 3.2 MHz) (35)
tSCLKH
141
ns
SCLK Clock Low Time (SCLK = 3.2 MHz) (35)
tSCLKL
141
ns
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
Required Setup Time (35)
tLEAD
140
ns
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
Required Setup Time (35)
tLAG
50
ns
SI, CS, SCLK Incoming Signal Rise Time (35)
tRSI
50
ns
SI, CS, SCLK Incoming Signal Fall Time (35)
tFSI
50
ns
Notes
27.
Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15
Ω resistive load to a V
BAT
of 15 V, VPWR = 15 V.
28.
Output Turn-ON Delay Time measured from rising edge (3.0 V) VIN (CS for serial) to 90% VO using a 15 Ω load to a VBAT of 15 V,
VPWR = 15 V.
29.
Output Turn-OFF Delay Time measured from falling edge (1.0 V) VIN (3.0 V rising edge of CS for serial) to 10% VO using a 15 Ω load
to a VBAT of 15 V, VPWR = 15 V.
30.
The shorted output is turned ON during tSS to retry and check if the short has cleared. The shorted output is in current limit during tSS.
The tSS is measured from the start of current limit to the end of current limit.
31.
The Short Fault Refresh Time is the waiting period between tSS retry signals. The shorted output is disabled during this refresh time.
The tREF is measured from the end of current limit to the start of current limit.
32.
The tOS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100
µs after the faulted output is off.
33.
The tOS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
34.
Percent Output Short Fault ON Duty Cycle is defined as (tSS) ÷ (tREF) x 100. This specification item is provided FYI and is not tested.
35.
Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.


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