WS128J0PBFI10 datasheet(5/97 Pages) SPANSION

Part #	WS128J0PBFI10

Description	128/64 Megabit (8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

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Manufacturer	SPANSION [SPANSION]

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May 11, 2006 S29WS-J_00_A6

S29WS128J/064J

5

D a ta

Sh eet

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 70

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 11. Test Setup ......................................................... 71

Table 21. Test Specifications ............................................... 71

Key to Switching Waveforms . . . . . . . . . . . . . . . 71

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 71

Figure 12. Input Waveforms and Measurement Levels............. 71

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 72

VCC Power-up ......................................................................................................72

Figure 13. VCC Power-up Diagram ........................................ 72

CLK Characterization ........................................................................................72

Figure 14. CLK Characterization ........................................... 72

Synchronous/Burst Read ...................................................................................73

Figure 15. CLK Synchronous Burst Mode Read (rising active CLK).

....................................................................................... 74

Figure 16. CLK Synchronous Burst Mode Read (Falling Active Clock)

....................................................................................... 75

Figure 17. Synchronous Burst Mode Read.............................. 75

Figure 18. 8-word Linear Burst with Wrap Around................... 76

Figure 19. Linear Burst with RDY Set One Cycle Before Data.... 76

Asynchronous Mode Read ...............................................................................77

Figure 20. Asynchronous Mode Read with Latched Addresses... 77

Figure 21. Asynchronous Mode Read..................................... 78

Hardware Reset (RESET#) .............................................................................. 78

Figure 22. Reset Timings..................................................... 79

Erase/Program Operations .............................................................................80

Figure 23. Asynchronous Program Operation Timings: AVD#

Latched Addresses ............................................................. 81

Figure 24. Asynchronous Program Operation Timings: WE# Latched

Addresses ......................................................................... 82

Figure 25. Synchronous Program Operation Timings: WE# Latched

Addresses ......................................................................... 83

Figure 26. Synchronous Program Operation Timings: CLK Latched

Addresses......................................................................... 84

Figure 27. Chip/Sector Erase Command Sequence ................. 85

Figure 28. Accelerated Unlock Bypass Programming Timing..... 86

Figure 29. Data# Polling Timings (During Embedded Algorithm) 86

Figure 30. Toggle Bit Timings (During Embedded Algorithm) ... 87

Figure 31. Synchronous Data Polling Timings/Toggle Bit Timings 87

Figure 32. DQ2 vs. DQ6...................................................... 88

Temporary Sector Unprotect ........................................................................88

Figure 33. Temporary Sector Unprotect Timing Diagram ......... 88

Figure 34. Sector/Sector Block Protect and Unprotect Timing

Diagram ........................................................................... 89

Figure 35. Latency with Boundary Crossing ........................... 89

Figure 36. Latency with Boundary Crossing into Program/Erase Bank

........................................................................................90

Figure 37. Example of Wait States Insertion .......................... 91

Figure 38. Back-to-Back Read/Write Cycle Timings................. 92

Erase and Programming Performance . . . . . . . . 93

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 94

VBH084 - 84-ball Fine-Pitch Ball Grid Array (FBGA) 8x11.6 mm MCP

Compatible Package (128Mb) ..........................................................................94

VBR080 - 80-ball Fine-Pitch Ball Grid Array (FBGA) 7 x 9 mm (64Mb)

................................................................................................................................... 95

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 96

Revision A0 (July 22, 2004) .............................................................................96

Revision A1 (October 6, 2004) .......................................................................96

Revision A2 (December 10, 2004) .................................................................96

Revision A3 (February 19, 2005) ....................................................................96

Revision A4 (June 24, 2005) ............................................................................96

Revision A5 (March 31, 2006) .........................................................................96

Revision A6 (April 28, 2006) .......................................................................... 97

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