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MBM29BS32LF18PBT Datasheet(PDF) 3 Page - SPANSION |
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MBM29BS32LF18PBT Datasheet(HTML) 3 Page - SPANSION |
3 / 60 page MBM29BS/BT32LF-18/25 3 s s s s FEATURES •0.17 µµµµm process technology • Single 1.8 volt read, program and erase (1.65 V to 1.95 V) • Simultaneous Read/Write operation (Dual Bank) • All Sectors Being Protected Upon Power-up The device aims for high-speed read of stored codes, thus to fully prevent it from much anticipated wrong operational procedures, programming and erasure, it adopts All-Sectors Lock for ultimate all sector protection by default upon power-up. • FlexBankTM *1 Bank A: 8M bit (8K words × 4 and 32K words × 15) Bank B: 8M bit (32K words × 16) Bank C: 8M bit (32K words × 16) Bank D: 8M bit (8K words × 4 and 32K words × 15) • Enhanced I/OTM *2 (VCCQ) Feature Input/ Output voltage generated on the device is determined based on the VI/O level (MBM29BS32LF: 1.8V VCCQ and MBM29BT32LF: 3.0V VCCQ) • High Performance Burst frequency reach at 54MHz Burst access times of 13.5 ns @ 30 pF at industrial temperature range Asynchronous random access times of 70 ns (at 30 pF) Synchronous latency of 106 ns with 1.8 V VCCQ, and 106.5 ns with 3.0 V VCCQ (at 30 pF) • Programmable Burst Read Interface Linear Burst: 8, 16, and 32 words with wrap-around • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Minimum 100,000 program/erase cycles • Sector Erase Architecture Eight 8K words, sixty-two 32K words sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Write Protect Pin (WP) At VIL, allows protection of “outermost” 2 × 8K words on low end of boot sectors(SA0 and SA1), regardless of sector protection/unprotection status • Accelerate Pin (ACC) At VACC, increases program performance. At VIL, hardware protect method to lock all sectors. • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address •Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • In accordance with CFI (Common Flash Interface) • Hardware reset pin (RESET) Hardware method to reset the device for reading array data To avoid initiation of a write cycle during Vcc power-up/down, Reset must be VIL for defined time. (Continued) |
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