Philips Semiconductors Programmable Logic Devices

Product specification

PLUS173–10

Programmable logic array

(22

× 42 × 10)

October 22, 1993

46

LOGIC PROGRAMMING

The PLUS173–10 is fully supported by

industry standard (JEDEC compatible) PLD

CAD tools, including Philips Semiconductors

SNAP design software package. ABEL

™ and

CUPL

™ design software packages also

support the PLUS173–10 architecture.

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic

capture format.

PLUS173–10 logic designs can also be

generated using the program table entry

format, which is detailed on the following

page. This program table entry format is

supported by SNAP only.

To implement the desired logic functions, the

state of each logic variable from logic

equations (I, B, O, P, etc.) is assigned a

symbol. The symbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc.,

are defined below.

PROGRAMMING AND

SOFTWARE SUPPORT

Refer to Section 9

(Development Software)

and Section 10

(Third-party Programmer/

Software Support) of this data handbook for

additional information.

AND ARRAY – (I, B)

CODE

O

STATE

INACTIVE1, 2

CODE

STATE

CODE

STATE

CODE

STATE

I, B

H

L

–

P, D

I, B

I, B

I, B

I, B

P, D

I, B

I, B

I, B

P, D

I, B

I, B

I, B

P, D

I, B

I, B

I, B

DON’T CARE

OR ARRAY – (B)

VIRGIN STATE

A factory shipped virgin device contains all

fusible links intact, such that:

1. All outputs are at “H” polarity.

NOTES:

1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused

(I, B) are left intact.

ABEL is a trademark of Data I/O Corp.

CUPL is a trademark of Logical Devices, Inc.

CODE

ACTIVE LEVEL

LOW

(INVERTING)

L

CODE

ACTIVE LEVEL

HIGH1

(NON-INVERTING)

H

S

X

B

S

X

B

OUTPUT POLARITY – (B)

CODE

INACTIVE

A

CODE

Pn STATUS

ACTIVE1

•

P

S

Pn STATUS

P

S