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PLHS501I Datasheet(PDF) 1 Page - NXP Semiconductors |
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PLHS501I Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 12 page  47 48 49 50 51 52 33 32 31 29 30 28 27 26 25 24 23 22 21 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 10 9 8 34 35 36 37 38 39 40 41 42 43 44 45 46 1 A Package (52-pin PLCC) I11 I12 I10 I13 I14 I15 I16 I17 I9 I8 I7 I6 I5 VCC I4 I3 I2 I1 I0 B3 B2 B1 B0 X7 X6 GND GND X5 X4 X3 X2 X1 X0 O7 O6 O5 O4 O3 O2 O1 O0 B7 B6 B5 B4 I23 I22 I21 I20 I19 I18 VCC Philips Semiconductors Programmable Logic Devices Product specification PLHS501/PLHS501I Programmable macro logic PML ™ 1 October 22, 1993 853–1207 11164 FEATURES • Programmable Macro Logic device • Full connectivity • TTL compatible • SNAP development system: – Supports third-party schematic entry formats – Macro library – Versatile netlist format for design portability – Logic, timing, and fault simulation • Delay per internal NAND function = 6.5ns (typ) • Testable in unprogrammed state • Security fuse allows protection of proprietary designs STRUCTURE • NAND gate based architecture – 72 foldback NAND terms • 136 input-wide logic terms • 44 additional logic terms • 24 dedicated inputs (I 0 – I23) • 8 bidirectional I/Os with individual 3-State enable: – 4 Active-High (B4 – B7) – 4 Active-Low (B0 – B3) • 16 dedicated outputs: – 4 Active-High outputs O0, O1 with common 3-State enable O2, O3 with common 3-State enable – 4 Active-Low outputs: O4, O5 with common 3-State enable O6, O7 with common 3-State enable – 8 Exclusive-OR outputs: X0, X1 with common 3-State enable X2, X3 with common 3-State enable X4, X5 with common 3-State enable X6, X7 with common 3-State enable PIN CONFIGURATION DESCRIPTION The PLHS501 is a high-density Bipolar Programmable Macro Logic device. PML incorporates a programmable NAND structure. The NAND architecture is an efficient method for implementing any logic function. The SNAP software development system provides a user friendly environment for design entry. SNAP eliminates the need for a detailed understanding of the PLHS501 architecture and makes it transparent to the user. PLHS501 is also supported on the Philips Semiconductors SNAP software development systems. The PLHS501 is ideal for a wide range of microprocessor support functions, including bus interface and control applications. The PLHS501 is also processed to industrial requirements for operation over an extended temperature range of –40 °C to +85°C and supply voltage of 4.5V to 5.5V. ARCHITECTURE The core of the PLHS501 is a programmable fuse array of 72 NAND gates. The output of each gate folds back upon itself and all other NAND gates. In this manner, full connectivity of all logic functions is achieved in the PLHS501. Any logic function can be created within the core of the device without wasting valuable I/O pins. Furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the I/O buffers. PML is a trademark of Philips Semiconductors |
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