Quad Bias Driver for GaAs FET and PIN Diode Switches

MADRMA0001 & 2

MADR-007690-DR0002

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5

Application Information

•

The input logic voltage (V in) cannot exceed the positive supply (Vcc) by more than 0.5 V nor go be-

low GND by more than 0.5 V.

•

The input current should not exceed ± 25 mA.

•

This device should be treated as any TTL CMOS circuit. Pull-up/down resistors should tie to Vcc or

GND. Non-used inputs must be tied to GND. Decoupling caps (0.1 uF) should be used on Vcc and

Vee, and the output current should be limited to ± 40 mA.

•

Logic “0” sets J0 to J1 to low loss state

•

Limiting Resistors (R2, R3) set for +/- 20 mA output current

•

The value of the limiting resistors (R2, R3) is determined by the following: R1 = [(Vcc - Vdiode)/I de-

sired] - Rout

Driving FET Switches:

Driving PIN Diode Switches: