Philips Semiconductors

Objective specification

PowerMOS transistor

PHX5N50E

Isolated version of PHP8N50E

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

field-effect power transistor in a full

pack, plastic envelope featuring high

V

DS

Drain-source voltage

500

V

avalanche energy capability, stable

I

D

Drain current (DC)

4

A

blocking voltage, fast switching and

P

tot

Total power dissipation

30

W

high thermal cycling performance

R

DS(ON)

Drain-source on-state resistance

0.8

Ω

with low thermal resistance. Intended

for use in Switched Mode Power

Supplies (SMPS),

motor control

circuits

and

general

purpose

switching applications.

PINNING - SOT186A

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

case isolated

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

500

V

V

DGR

Drain-gate voltage

R

-

500

V

±V

GS

Gate-source voltage

-

30

V

I

D

Drain current (DC)

T

25 ˚C

-

4

A

T

-

2.5

A

I

DM

Drain current (pulse peak

T

25 ˚C

-

16

A

value)

I

DR

Source-drain diode current

T

25 ˚C

-

4

A

(DC)

I

DRM

Source-drain diode current

T

25 ˚C

-

16

A

(pulse peak value)

P

tot

Total power dissipation

T

25 ˚C

-

30

W

T

stg

Storage temperature

-55

150

˚C

T

j

Junction temperature

-

150

˚C

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

W

DSS

Drain-source non-repetitive

I

unclamped inductive turn-off

R

energy

T

-

510

mJ

T

-

82

mJ

W

DSR

1

Drain-source repetitive

I

-

13

mJ

unclamped inductive turn-off

R

energy

1. Pulse width and frequency limited by T

j(max)

12 3

case

d

g

s

November 1996

1

Rev 1.000