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AT32UC3A1512-AUT Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT32UC3A1512-AUT Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 52 page  4 32058AS–AVR32–03/07 3. Blockdiagram Figure 3-1. Blockdiagram UC CPU NEXUS CLASS 2+ OCD INSTR INTERFACE DATA INTERFACE TIMER/COUNTER INTERRUPT CONTROLLER REAL TIME COUNTER PERIPHERAL DMA CONTROLLER 512 KB FLASH HSB-PB BRIDGE B HSB-PB BRIDGE A S MM M M M S S S S S M EXTERNAL INTERRUPT CONTROLLER HIGH SPEED BUS MATRIX 64 KB SRAM PA PB PC PX A[2..0] B[2..0] CLK[2..0] EXTINT[7..0] KPS[7..0] NMI_N GCLK[3..0] XIN32 XOUT32 XIN0 XOUT0 PA PB PC PX RESET_N CAS RAS SDA10 SDCK SDCKE SDCS1 SDWE NCS[3..0] NRD NWAIT NWE0 DATA[15..0] USB INTERFACE DMA ID VBOF VBUS D- D+ ETHERNET MAC DMA 32 KHz OSC 115 kHz RCOSC OSC0 PLL0 PULSE WIDTH MODULATION CONTROLLER USART3 SERIAL PERIPHERAL INTERFACE 0/1 TWO-WIRE INTERFACE RXD TXD CLK MISO, MOSI NPCS[3..1] PWM[6..0] SCL SDA USART1 RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI USART0 USART2 RXD TXD CLK RTS, CTS SYNCHRONOUS SERIAL CONTROLLER TX_CLOCK, TX_FRAME_SYNC RX_DATA TX_DATA RX_CLOCK, RX_FRAME_SYNC ANALOG TO DIGITAL CONVERTER AD[7..0] ADVREF WATCHDOG TIMER XIN1 XOUT1 OSC1 PLL1 SCK JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N TCK TDO TDI TMS POWER MANAGER RESET CONTROLLER ADDR[23..0] SLEEP CONTROLLER CLOCK CONTROLLER CLOCK GENERATOR COL, CRS, RXD[3..0], RX_CLK, RX_DV, RX_ER MDC, TXD[3..0], TX_CLK, TX_EN, TX_ER, SPEED MDIO CONFIGURATION REGISTERS BUS MEMORY PROTECTION UNIT PB PB HSB HSB NWE1 NWE3 NPCS0 |
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