Philips Semiconductors

Product specification

N-channel TrenchMOS

™ transistor

PHW80NQ10T

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

V

• Fast switching

• Low thermal resistance

I

R

GENERAL DESCRIPTION

PINNING

SOT429 (TO247)

N-channel

enhancement

mode

PIN

DESCRIPTION

field-effect power transistor in a

plastic envelope using ’trench’

1

gate

technology.

2

drain

Applications:-

• d.c. to d.c. converters

3

source

• switched mode power supplies

tab

drain

The PHW80NQ10T is supplied in

the SOT429 (TO247) conventional

leaded package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DSS

Drain-source voltage

T

-

100

V

V

DGR

Drain-gate voltage

T

-

100

V

V

GS

Gate-source voltage

-

± 20

V

I

D

Continuous drain current

T

-

80

A

T

-

57

A

I

DM

Pulsed drain current

T

-

320

A

P

D

Total power dissipation

T

-

263

W

T

Operating junction and

- 55

175

˚C

storage temperature

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

E

AS

Non-repetitive avalanche

Unclamped inductive load, I

-

481

mJ

energy

t

V

to fig:15

I

AS

Non-repetitive avalanche

-

80

A

current

d

g

s

2

3

1

August 1999

1

Rev 1.000