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PHT6N03LT Datasheet(PDF) 1 Page - NXP Semiconductors |
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PHT6N03LT Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 6 page Philips Semiconductors Product specification TrenchMOS ™ transistor PHT6N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA • ’Trench’ technology V DSS = 30 V • Very low on-state resistance • Fast switching I D = 5.9 A • Stable off-state characteristics • High thermal cycling performance R DS(ON) ≤ 30 mΩ (VGS = 5 V) • Surface mounting package R DS(ON) ≤ 28 mΩ (VGS = 10 V) GENERAL DESCRIPTION PINNING SOT223 N-channel enhancement mode PIN DESCRIPTION logic level field-effect power transistor using ’trench’ 1 gate technology. The device has very low on-state resistance. It is 2 drain intended for use in dc to dc converters and general purpose 3 source switching applications. tab drain The PHT6N03LT is supplied in the SOT223 surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = 25 ˚C to 150˚C - 30 V V DGR Drain-gate voltage T j = 25 ˚C to 150˚C; RGS = 20 kΩ -30 V V GS Gate-source voltage - ± 13 V I D Continuous drain current T amb = 25 ˚C; V GS = 10 V - 5.9 A T amb = 100 ˚C; VGS = 10 V - 4.1 A I DM Pulsed drain current - 23.6 A P D Total power dissipation T amb = 25 ˚C - 1.8 W T j, Tstg Operating junction and - 55 150 ˚C storage temperature ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V C Electrostatic discharge Human body model (100 pF, 1.5 k Ω)- 2 kV capacitor voltage, all pins THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-sp Thermal resistance junction mounted on any pcb - - 15 K/W to solder point R th j-a Thermal resistance junction mounted on test pcb of fig:17 - 70 - K/W to ambient d g s 4 1 23 January 1998 1 Rev 1.300 |
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