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LH28F320BFB-PBTL60 Datasheet(PDF) 11 Page - Sharp Corporation |
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LH28F320BFB-PBTL60 Datasheet(HTML) 11 Page - Sharp Corporation |
11 / 37 page LHF32FB7 9 Rev. 2.44 NOTES: 1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but cannot be altered. 2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2 voltages. 3. RST# at GND±0.2V ensures the lowest power consumption. 4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when VPP=VPPH1/2 and VCC=2.7V-3.6V. 5. Refer to Table 6 for valid DIN during a write operation. 6. Never hold OE# low and WE# low at the same timing. 7. Refer to Appendix of LH28F320BF series for more information about query code. 8. RY/BY# is VOL when the WSM (Write State Machine) is executing internal block erase, full chip erase, (page buffer) program or OTP program algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend mode, or reset mode. Table 5. Bus Operation(1, 2) Mode Notes RST# CE# OE# WE# Address VPP DQ0-15 RY/BY# (8) Read Array 6 VIH VIL VIL VIH XX DOUT X Output Disable VIH VIL VIH VIH X X High Z X Standby VIH VIH X XXX High Z X Reset 3 VIL X X X X X High Z High Z Read Identifier Codes/OTP 6 VIH VIL VIL VIH See Table 3 and Table 4 X See Table 3 and Table 4 X Read Query 6,7 VIH VIL VIL VIH See Appendix X See Appendix X Write 4,5,6 VIH VIL VIH VIL XX DIN X |
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