Philips Semiconductors

Product specification

PowerMOS transistor

PHP3N20L

Logic level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode logic

SYMBOL

PARAMETER

MAX.

UNIT

level field-effect power transistor in a

plastic

envelope

featuring

high

V

DS

Drain-source voltage

200

V

avalanche energy capability, stable

I

D

Drain current (DC)

3.5

A

blocking voltage, fast switching and

P

tot

Total power dissipation

50

W

high thermal cycling performance

R

DS(ON)

Drain-source on-state resistance

1.5

Ω

with low thermal resistance. Intended

for use in Switched Mode Power

Supplies (SMPS),

motor control

circuits

and

general

purpose

switching applications.

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I

D

Continuous drain current

T

-

3.5

A

T

-

2.5

A

I

DM

Pulsed drain current

T

-

14

A

P

D

Total dissipation

T

-

50

W

∆P

Linear derating factor

T

-

0.33

W/K

V

GS

Gate-source voltage

-

± 15

V

V

GSM

Non-repetitive gate-source

t

± 20

V

voltage

E

AS

Single pulse avalanche

V

-

25

mJ

energy

V

I

AS

Peak avalanche current

V

-

3.5

A

V

T

Operating junction and

- 55

175

˚C

storage temperature range

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-mb

Thermal resistance junction to

-

3

K/W

mounting base

R

th j-a

Thermal resistance junction to

60

-

K/W

ambient

12 3

tab

d

g

s

September 1997

1

Rev 1.000