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DSP56858E Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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DSP56858E Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 64 page  Introduction 56858 Technical Data, Rev. 6 Freescale Semiconductor 9 Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. MODE A, MODE B and MODE C pins have no pull-up. 3. TCK has a weak pull-down circuit always active. 4. Bidirectional I/O pullups automatically disable when the output is enabled. This table is presented consistently with the Signals Identified by Functional Group figure. 1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Output(Z) means an output in a High-Z condition. Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type Description VDD E1 14 VDD Logic Power (VDD)—These pins provide power to the internal structures of the chip, and should all be attached to VDD. VDD M6 36 VDD F12 52 VDD A9 72 VDD M2 87 VDD J12 88 VDD E12 109 VDD A12 125 VSS G1 15 VSS Logic Power–Ground (VSS)—These pins provide grounding for the internal structures of the chip and should all be attached to VSS. VSS L6 16 VSS D12 53 VSS A7 54 VSS F1 71 VSS M7 89 VSS K12 126 VSS A8 127 |
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