PHW13N40E datasheet(2/10 Pages) PHILIPS

Part #	PHW13N40E

Description	PowerMOS transistors Avalanche energy rated

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product specification

PowerMOS transistors

PHP13N40E, PHB13N40E, PHW13N40E

Avalanche energy rated

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

E

AS

Non-repetitive avalanche

Unclamped inductive load, I

AS = 13.6 A;

-

705

mJ

energy

t

p = 0.2 ms; Tj prior to avalanche = 25˚C;

V

DD ≤ 50 V; RGS = 50 Ω; VGS = 10 V

E

AR

Repetitive avalanche energy

2

I

AR = 13.7 A; tp = 2.5 µs; Tj prior to

-

18

mJ

avalanche = 25˚C; R

GS = 50 Ω; VGS = 10 V

I

AS, IAR

Repetitive and non-repetitive

-

13.7

A

avalanche current

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction

-

0.8

K/W

to mounting base

R

th j-a

Thermal resistance junction

SOT78 package, in free air

-

60

-

K/W

to ambient

SOT429 package, in free air

-

45

-

K/W

SOT404 package, pcb mounted, minimum

-

50

-

K/W

footprint

ELECTRICAL CHARACTERISTICS

T

j = 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown

V

GS = 0 V; ID = 0.25 mA

400

-

V

voltage

∆V

(BR)DSS / Drain-source breakdown

V

DS = VGS; ID = 0.25 mA

-

0.1

-

%/K

∆T

j

voltage temperature

coefficient

R

DS(ON)

Drain-source on resistance

V

GS = 10 V; ID = 6.5 A

-

0.26

0.35

Ω

V

GS(TO)

Gate threshold voltage

V

DS = VGS; ID = 0.25 mA

2.0

3.0

4.0

V

g

fs

Forward transconductance

V

DS = 30 V; ID = 6.5 A

4

7.5

-

S

I

DSS

Drain-source leakage current V

DS = 400 V; VGS = 0 V

-

1

25

µA

V

DS = 320 V; VGS = 0 V; Tj = 125 ˚C

-

50

500

µA

I

GSS

Gate-source leakage current V

GS = ±30 V; VDS = 0 V

-

10

200

nA

Q

g(tot)

Total gate charge

I

D = 13 A; VDD = 320 V; VGS = 10 V

-

79

100

nC

Q

gs

Gate-source charge

-

7.2

12

nC

Q

gd

Gate-drain (Miller) charge

-

43

55

nC

t

d(on)

Turn-on delay time

V

DD = 200 V; RD = 15 Ω;

-

16

-

ns

t

r

Turn-on rise time

R

G = 5.6 Ω

-40

-

ns

t

d(off)

Turn-off delay time

-

100

-

ns

t

f

Turn-off fall time

-

42

-

ns

L

d

Internal drain inductance

Measured from tab to centre of die

-

3.5

-

nH

L

d

Internal drain inductance

Measured from drain lead to centre of die

-

4.5

-

nH

(SOT78 package only)

L

s

Internal source inductance

Measured from source lead to source

-

7.5

-

nH

bond pad

C

iss

Input capacitance

V

GS = 0 V; VDS = 25 V; f = 1 MHz

-

1283

-

pF

C

oss

Output capacitance

-

218

-

pF

C

rss

Feedback capacitance

-

120

-

pF

2 pulse width and repetition rate limited by T

j max.

December 1998

2

Rev 1.000

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