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DSP56852 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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DSP56852 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 48 page  Introduction 56852 Technical Data, Rev. 8 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56852 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or signals present. 1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. CLKOUT is muxed Address pin A20. 3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins. 4. CS3 is multiplexed with external Address Bus pin A19. 5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18. 6. Four of these pins are multiplexed with SSI. 7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Power (VDD, VDDIO, or VDDA) 101 Ground (VSS, VSSIO,or VSSA) 101 Phase Lock Loop (PLL) and Clock 22 External Bus Signals 393 External Chip Select* 34 Interrupt and Program Control 35 Synchronous Serial Interface (SSI) Port* 6 Serial Communications Interface (SCI) Port* 2 Serial Peripheral Interface (SPI) Port 06 Quad Timer Module Port 07 JTAG/Enhanced On-Chip Emulation (EOnCE) 6 *Alternately, GPIO pins |
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