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DSP56F807PY80 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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DSP56F807PY80 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 60 page 56F807 Technical Data Technical Data, Rev. 15 8 Freescale Semiconductor Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F807 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-19, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Detailed Description Power (VDD or VDDA)11 Table 2-2 Ground (VSS or VSSA)13 Table 2-3 Supply Capacitors & VPP 4 Table 2-4 PLL and Clock 3 Table 2-5 Address Bus1 16 Table 2-6 Data Bus 16 Table 2-7 Bus Control 4 Table 2-8 Interrupt and Program Control 5 Table 2-9 Dedicated General Purpose Input/Output 14 Table 2-10 Pulse Width Modulator (PWM) Ports 26 Table 2-11 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins 4 Table 2-12 Quadrature Decoder Ports2 2. Alternately, Quad Timer pins 8 Table 2-13 Serial Communications Interface (SCI) Ports1 4 Table 2-15 CAN Port 2 Table 2-16 Analog to Digital Converter (ADC) Ports 20 Table 2-17 Quad Timer Module Ports 6 Table 2-18 JTAG/On-Chip Emulation (OnCE) 6 Table 2-19 |
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