Philips Semiconductors

Product specification

Dual N-channel enhancement mode

PHN203

TrenchMOS

FEATURES

SYMBOL

QUICK REFERENCE DATA

• Dual device

V

• Low threshold voltage

• Fast switching

I

• Logic level compatible

• Surface mount package

R

R

GENERAL DESCRIPTION

PINNING

SOT96-1

N-channel

enhancement

mode

PIN

DESCRIPTION

field-effect power transistor in a

plastic envelope using ’trench’

1

source 1

technology. The device has very

low

on-state

resistance.

It

is

2

gate 1

intended for use in dc to dc

converters and general purpose

3

source 2

switching applications.

4

gate 2

The PHN203 is supplied in the

SOT96-1 (SO8) surface mounting

5,6

drain 2

package.

7,8

drain 1

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Repetitive peak drain-source

T

-

25

V

voltage

V

DS

Continuous drain-source voltage

-

25

V

V

DGR

Drain-gate voltage

R

-25

V

V

GS

Gate-source voltage

-

± 20

V

I

D

Drain current per MOSFET

1

T

-

6.3

A

T

-

5

A

I

D

Drain current per MOSFET (both

T

-

4.4

A

MOSFETs conducting)

1

T

-

3.5

A

I

DM

Drain current per MOSFET (pulse

T

-

25

A

peak value)

P

tot

Total power dissipation (either or

T

-

2

W

both MOSFETs conducting)

1

T

-

1.3

W

T

Storage & operating temperature

- 55

150

˚C

d1

g1

s1

d1

d2

g2

d2

s2

12

34

5

6

7

8

pin 1 index

1 Surface mounted on FR4 board, t

≤ 10 sec

January 1999

1

Rev 1.000