2Mx36 & 4Mx18 DDRII CIO b4 SRAM

K7I643684M

K7I641884M

- 8 -

Rev. 1.3 March 2007

Detail Specification of Power-Up Sequence in DDRII SRAM

DDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep Doff at low state (All other inputs may be undefined)

- Apply VDD before VDDQ

- Apply VDDQ before VREF or the same time with VREF

2. Just after the stable power and clock(K,K), take Doff to be high.

3. The additional 2048 cycles of clock input is required to lock the DLL after enabling DLL

* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds

(Min. 30ns) to reset the DLL after it become a stable clock status.

1. DLL uses either K clock as its synchronizing input, the input should have low phase jitter which is specified as TK var.

2. The lower end of the frequency at which the DLL can operate is 120MHz.

3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency

and this may cause the failure in the initial stage.

Status

Power-Up

K,K

* Notes: When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 2048 cycles of clock input is needed to lock the DLL.

Unstable

CLKstage

1024 cycle

DLL Locking Range

Any

Command

Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)

K,K

Min 30ns

Doff

1024 cycle

Status

Power-Up

Unstable

CLKstage

DLL Locking Range

Any

Command

Stop Clock

Inputs Clock

must be stable

Power up & Initialization Sequence (Doff pin controlled)

Inputs Clock

must be stable